The present invention relates to a technique for multiplying binary numbers.
Circuits for multiplying binary numbers require a relatively large number of circuit elements and thus take up a fair amount of chip area when fabricated on an integrated circuit. For this reason, an ongoing goal of integrated circuit designers is to find ways to implement a multiplier circuit with fewer and fewer circuit elements.
For example, a technique that is in widespread use is to represent one of the two numbers being multiplied using so-called modified Booth encoding. This approach reduces, by a factor of two, the number of partial products generated by the multiplier, thereby reducing the amount of circuitry needed to combine the partial products in arriving at the final product. Unfortunately, the fact that signed binary numbers are typically represented using two's complement notation--at least when being operated on arithmetically--significantly dulls the above-described advantage of modified Booth encoding because of the need to perform so-called sign-bit extension of the partial products before they can be combined (as explained in further detail hereinbelow).